The Berkeley Intelligent RAM (IRAM) Project

The Berkeley Intelligent RAM (IRAM) project seeks to understand the entire spectrum of issues involved in designing general-purpose computer systems that integrate a processor and DRAM onto a single chip - from circuits, VLSI design and architectures to compilers and operating systems. IRAM should offer several advantages over today's solutions, including considerably reduced latency and dramatically increased bandwidth to main memory, reduced power and energy consumption, and reduced space and weight for embedded, portable, desktop, and parallel computer systems.
VIRAM1, the first Berkeley implementation of an IRAM chip, taped out in October, 2002.

Wafers are back, and have been packaged. Testing is proceeding. More information and photos are available.

Vector IRAM Documentation:

->  Overview Brief overview and history of the Berkeley IRAM project.
->  Publications and Talks from Hot Chips VII, ISSCC '97, ISCA '97, IEEE Micro, and related articles.
->  People Who we are and how to reach us.
->  Winter 2000 Retreat IRAM, ISTORE, and OceanStore talks at the Winter 2000 Retreat.
->  The IRAM Class Taught in the Spring of 1996 by Prof. David Patterson.
->  The ISTORE Project A project investigating introspective storage architectures for data-intensive network services.
->  Related Links Pointers to related projects and computer architecture information.

Restricted access...
->  Guest Directory For users of IRAM tools, and other guests.
->  Working Directory For IRAM group members only.

Contact: webmaster at
Computer Science Division
University of California at Berkeley