Interconnection Issues between Memory and Logic in IRAM Systems

5/13/97


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Table of Contents

Interconnection Issues between Memory and Logic in IRAM Systems

Introduction

Potential IRAM System Floorplan

Outline

Memory Bank Organization

Memory Bank Implementation

Traditional Interconnection of Banks

Memory Section Organization

Area Efficiency Considerations

Memory Area Considerations (Examples)

Memory Subsystem Interface

Memory Interface Commands

Pipeline Stages of Interface Commands

Memory Section Bus

Bus Schemes

Single-ended Bus Differential Bus

Low-swing Busses: Waveforms

Section Bus Simulation Results

Memory Crossbar

Crossbar Design Challenges

What about Buffers?

Energy Delay Product Vs Device Size

Energy Delay Product Vs Driver Strength

Crossbar Switch Layout

Section of Crossbar

Crossbar Alternatives

Large Fully-Connected Crossbar

Self Routing Crossbar

Self Routing Crossbar

Small Crossbar and Bus

Crossbar Area and Speed Results

Summary

Author: J. Golbus, B. Gribstad, C. Kozyrakis, K. Wang

Email: kozyraki@cs.berkeley.edu

Home Page: http://www.cs.berkeley.edu/~kozyraki/project/ee241