Memory Area Considerations (Examples)
Assuming a 20mm x 20 mm chip with 1/4 of the area for the processor
Case 1:
- Memory bank: 4x4 DRAM arrays, 4 row buffers
- 192 banks on-chip (2Mbits/bank) organized as 32 sections with 6 banks per section or 16 sections with 12 banks per section etc
- Area efficiency: 74%
Case 2:
- Memory bank: 8x8 DRAM arrays, 4 row buffers
- 48 banks on-chip (8Mbit/bank) organized as 8 sections with 3 banks per section
- Area efficiency: 75%