Interconnect between processor and memory in IRAM systems is required to provide high bandwidth and low latency, while achieving high energy efficiency. In this work, we address circuit and architectural issues of the processor-memory interconnect by studying its two basic components: the memory subsystem and the processor-memory crossbar. We propose a new architecture for the on-chip DRAM that enables high bandwidth at low energy cost. We examine in detail the structure, area and performance of three crossbar alternatives that allow full connectivity between the processor and the memory. Finally, we performed detailed simulations of bus schemes, including low-swing and differential, to evaluate their characteristics and efficiency in a DRAM process.