In this work we addressed a number of issues about the processor memory interconnect in IRAM systems. We proposed a new DRAM architecture, where buses are routed on-top of the memory array to enable high bandwidth at low area and energy penalty. This architecture also provides caching. We evaluated the characteristics of four bus schemes in a DRAM process and realized that low-swing buses offer significant advantages both in terms of delay and power. When the number of wires is not an issue, differential signaling provides additional benefits. We examined in details three different crossbar structures appropriate for connecting the processor to the memory subsystem and quantified the tradeoff between area, delay and energy for the these designs.
This study is by no means complete. For the memory architecture, a performance oriented evaluation and a prototype implementation are necessary to prove its potential advantages and feasibility. For the crossbar, this work provides information about the tradeoffs, the circuit details and the basic limitations associated with each alternative design and can be used as a starting point or reference for an actual implementation.