With the area and power estimates we currently have, a package could be selected if we had a pin count estimate. Of course, if the technology we are using changes the area and power estimates may change somewhat. A sample floorplan could then be created once the pad locations are known.
When deciding what pins to bring off the chip it is important to consider what issues may be faced in a testing situation. We would like to have control over all the feedback loops in the link from outside the chip. If they work fine, we can connect the proper pins externally. If a given feedback loop doesn't work as expected, however, we can still obtain useful data. For example, if the transmit DLL loop doesn't properly lock, we can set the control voltage manually to produce the desired delay between clocks if the control voltage is brought off chip. This is a very sensitive node, so a large capacitor will be required as a loop filter and a large charge pump current will be necessary for reasonable lock time. Thus there are tradeoffs when designing for a test chip situation.
The feedback loops that we are interested in opening up to outside control are the two DLLs and the receiver tracking loop. Also, we would like to see the data after encoding, the input to the phase interpolator, the the data on the differential signal lines, the data after sampling, the data after decoding, and possibly the clocks from each of the DLLs. Also, critical status signals such as the bit lock and byte lock signals should also be available off chip. All of these pins can quickly add up. We need to consider which signals will offer the most insight for debugging purposes and which we can get by without.
In comparison with IC's similar to this project, our estimates appear to fit quite well. Power dissipation of a 0.8 mm2 two DLL device in a 1um process (drawn) and 3.3V was 102mW at 250MHz [Sid97]. This device consisted of only DLLs, a small amount of digital control, and a noise generator. A CMOS serial link with 4x oversampling consumed 425 mW at 100MHz, 5V, and was fabricated in 1.2um CMOS with an area of 9 mm2 [Lee95]. An oversampling transceiver with a 5V supply, 0.8 um CMOS, 9 mm2 consumes 1 Watt of power [Yan96]. Our estimates of 0.5 mm2 and 83 mW of power are reasonable considering the technology we are using in 0.4um CMOS (drawn) and the supply is 3.3V. Our estimates do not include loop filters (capacitors) for the DLLs. Another thing to remember is that most of the reported transceivers do not have an encoder/decoder.