Power and Area Summary

The complete layout of all portions of the design has yet to be assembled. The following table gives a breakdown of which components are contributing the most power (under typical operating conditions) and the area of each block.

Transmit DLL15.3mW24834um2
Receive DLL16.2mW21304um2
Phase Interpolator5.6mW57000um2
Samplers240uA x 20 => 23.7mW9000um2
Bit Lock3mW32000um2
Byte Lock-32400um2
Transmit Control-70000um2
Retiming Registers-66000um2

Total Power Consumption for Typical Operation

It can be seen that the analog circuitry in this design dominates the power consumption due to the static current inherent in the designs. One method that could be used to reduce the power is to set a specific speed requirement for the link, say 1 Gbit/s. If more bandwidth is required from a link, more links can be run in parallel and synchronized at a higher level, as stated earlier. We could then reduce the number of analog elements by a factor of 2 and run them at twice the rate, since we don't have to worry about making the link run faster than intended. We could build a 1 Gbit/s link with only 5 delay elements in the delay lines, and thus half the samplers and half the latches, and run it at twice the rate. Fewer delay elements also means less inherent jitter from the DLLs. This would impose a smaller timing window for all of the digital logic, however. Instead of a 10 ns cycle time, only 5 ns would now be available. We need to further examine the delays of the current digital logic blocks to see if this is possible.