References

[Cha97] Chang, K. et.al., "A 2 Gb/s Asymmetic Serial Link for High-Bandwidth Packet Switches," Proceedings of Hot Interconnects Symposium V, pp. 157-169, Stanford University, August 21-23, 1997.

[Dal97] Dally, W., Poulton, J., Tell, S., "A Tracking Clock Recovery Receiver for 4 Gb/s Signaling," Proceedings of Hot Interconnects Symposium V, pp. 171-179, Stanford University, August 21-23, 1997.

[Enam92] Enam, S. and Abidi, A. "NMOS IC's for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers,"  IEEE Journal of Solid State Circuits, vol. 27, no. 12, Dec. 1992.

[Hor93] Horowitz, M. and Maneatis, J., "Precise Delay Generation Using Coupled Oscillators," IEEE Journal of Solid-State Circuits, V. 28, No. 12, December 1993.

[Lee95] Lee, K. et.al., "A CMOS Serial Link for Fully Duplexed Data Communication," IEEE Journal of Solid-State Circuits, V. 30, No. 4, April 1995.

[Man96] Maneatis, J., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, V. 31, No. 11, November 1996.

[Sid97] Sidiropoulos, S. and Horowitz, M., "A Semi-Digital Dual Delay Locked Loop," IEEE Journal of Solid-State Circuits, V. 32, No. 11, November 1997.

[Wid83] Widmer, A. and Franaszek, P., "A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code," IBM J. Res. Develop., Vol. 27, No. 5, September 1993.

[Yan96] Yang, C. and Horowitz, M., "A 0.8-um CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links" IEEE Journal of Solid-State Circuits, V. 31, No. 12, December 1996.

[You92] Young, I. et.al., "A PLL Clock Generator with 5 to 110 MHz Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits, V. 27, No. 11, November 1992.