Figure 2.6.1 - Channel Model
Introduction
The transmitter and receiver pair are designed to provide reliable 1Gbit/s transmission with optimization for power consumption and insensitivity to package parasitics. Many amplifier structures were investigated, including a structure commonly used in published work [Dal97]. This structure uses a common source, class A transmitter stage to provide a current mode (high impedance) output. This current is terminated on the receiver either by 50 Ohm resistors on the PC board or by the low-impedance input of a common gate (cascode) amplifier on the receiver chip. This amplifier topology provides good performance until a model for the package parasitics is inserted into the system. A simple model of the pad to pad network is shown below.
The bond wire inductance and pad/pin capacitance form a resonant/reactive circuit. More accurately, this network can be viewed as a LC ladder filter. If we generalize all transmitter receiver topologies in 4 catagories - current/current, current/voltage, voltage/current, and voltage/voltage - we can represent these as four ladder networks with different terminations. Current mode indicates high source or load impedance, and voltage mode indicates low impedance. The terminating impedances in ladder networks alter the filter response. The magnitude and phase response of this filter affect the level of pulse distortion at the receiver. A significant problem for digital systems is the group delay, that can be adversely affected by the LC filter. To examine the affect of this network on different amplifier topologies, we can similate different ladder networks and use 50 Ohm impedance for the voltage mode and ideal current sources for current mode, and examine the voltage developed accross the load resistor. The magnitude and phase response for these networks are shown below.
The package parasitics result in superior performance from a voltage/voltage amplifier topology where the terminating impedances are low. Other simulations indicated that the bandwidth/power value is better for the voltage/voltage topology.
Given this design, a class AB structure was initially investigated in an attempt to reduce power consumption. To exploit this design with a resistive termination at the receiver, a multi-level transition based signaling scheme was required. Specifically, if there is a positive transition, send a positive pulse, or negative transition, send a negative pulse. Otherwise, the line remains balanced. Unfortunately, all the extra circuits required to make this system work outweighed the power savings in the core amplifier. Accordingly, a class A structure was adopted with regular digital signaling.
A balanced design is used because of the reduced sensitivity to supply noise and other EM interference. The dominant noise source is expected to be digital noise coupled through the bond-wire mutual inductance. Again, the digital design offers lower sensitivity, especially if the noise pads are a reasonable distance from the link pads.
The transmitter design is based around a common-drain amplifier (source follower). Devices M0-M1 buffer the input before driving output devices M2-M3. The output current of 3mA is set by current source M5. The DC path for the output devices is provided by the input devices of the receiver. This design is insensitive to supply noise because the voltage VDN in is independant of VDDA or VSSA of the transmitter. This value is (Vgsp + Vgsn) above VSSA of the negative supply of the receiver. The load resistors are used in place of MOS devices because a reliable resistor cannot be made without a fixed supply, and node VDN moves with process and temperature.
The output device sizing is driven by a desired 50 Ohm output impedance (single ended) and a Vdsat operating point to enable high speed operation. The cutoff frequency of the device is proportional to Vdsat. The tradeoff exists between cutoff frequency and power consumption for a given output impedance. Furthermore, the large signal behavior of the circuit is referenced to Vdsat, so that the operation remains linear for a larger voltage swing for higher vdsat. This keeps the output impedance more constant during switching than with a larger device and smaller Vdsat.
The preamplifier section is as simple differential input pair with source follower output that provides a flexible, low-capacitance input for the serializer. The resistive loads are implemented with PMOS transistors in triode region. The voltage swing of this stage determines the operating range for the transmitter. This can be adjusted by varying the control voltage VBPR that changes the load resistance.
The receiver is based on a common-gate amplifier (cascode). The input devices M0-M1 provide a low-impedance input. The input impedance of these devices is approximately 50 Ohms (single-ended). These devices convert the received voltage to a current that is converted back to a voltage by the load resistors. The 3dB bandwidth at the drain of the input devices is greater than 2GHz, to reduce pulse distortion. This output is buffered by source followers. The Vgs of these devices is designed to be greater than Vdsat + Vgs of the NMOS input devices in the following stage.
The long-channel triode devices M2-M3 provide a DC bias for the PMOS well without affecting the AC performance of the input devices. This bias eliminates the body effect for these devices, improving headroom.
The postamplifier provides gain and buffering of the received signal. It is designed to drive the input capacitance of the 20-unit sampler, as well as amplify the received signal with a small-signal gain of approximately 10.
The bias circuitry for both the transmitter and receiver is generated by replica biasing. The unit current is 50uA and is provided by an on-chip band gap reference with PTAT for temperature compensation. The current sources in the various blocks use multiple instances of this device, and the Vdsat of the unit device is large for improved current matching in the presence of voltage drops between subcircuit VSSA. The total current consumption for the transceiver including all support amplifiers is 5mA.
The transceiver was simulated using the package parasitic model described earlier. These parasitics were compiled from various professional sources and appear to be a reasonable estimate. However, they dominate the transmission behavior and should be amended if more accurate package details become available. The tranceiver operation was tested with a 2Gb/s input and worst-case simulation models.
The input sequence was designed to investigate pulse-distortion and intersymbol interference (ISI). A string of ones with either one or two zeros was sent. The resulting transitions were examined from data-dependant transition movement. Below is a sample of the results.
The eye is approximately 400ps wide in the worst case (single zero) and varies by approximately 50ps with data dependance. This value can be decreased by increasing the system bandwidth or by providing a channel equalizer. The latter is an attractive solution to reducing ISI and considered in [Dal97]. A simple adaptive equalizer will be investigated before the chip is fabricated.
Twenty sampling units are required for proper receiver operation; ten units sample data and ten units sample transitions to provide inputs for the phase interpolator loop. The design objectives for the sampling units are to minimize power and area while providing sufficiently high gain to mitigate metastability issues. Metastability is a concern in this design because half of the samplers are triggering at or near data transitions. Metastability can be resolved with a large amount of gain. In an open loop system at this operating frequency, many stages of amplification would be required. To reduce the power and are associated with this approach, a positive-feedback source coupled latch topology was used. The circuit diagram is shown below.
The positive feedback provides very high gain in a single stage. However, the input -referred offset voltage of the latch is higher than that of an amplifier. This is a secondary concern in this application because 16 phase resolution of the phase interpolator dominates the error sources in the control loop. Nevertheless, the offset voltage of the latch was reduced by using large devices with small Vdsat, so that the offset voltage is approximately the Vt mismatch. The biasing for the circuit is provided by the tranceiver bias.
The latch is followed by a level converter. The circuit diagram, shown below, shows a basic PMOS differential pair with a NMOS push-pull output to convert to single ended CMOS levels. The input source follower are sized with a Vgs that is greater than Vgs+Vdsat of the PMOS input devices and current source. The circuit does not provide full switching, but does provide levels sufficient for an inverter buffer.
The sampling block was simulated in conjunction with the tranceiver simulation. The clock edges were generated with sources designed to replicate the DLL. The data input mentioned above was used. The input and digital output is shown below.
