Final Program
Workshop on Mixing Logic and DRAM:
Chips that Compute and Remember

Sunday, June 1st, 1997, 8:30am-5:30pm
Denver, Colorado

Organized as part of the 24th Annual International Symposium on Computer Architecture

This workshop was orgzanized as part of ISCA '97, and was held in the same location (the Westin Hotel, Tabor Center, in downtown Denver, Colorado) immediately before the conference. Registration for the workshop was via your ISCA registration.

For those interested in this workshop topic, you may also be interested in the half-day seminar presented by Steven Przybylski entitled Embedded DRAMs: Today and Toward System-Level Integration. This seminar took place on Saturday, May 31, 1997.

Schedule

The following schedule includes links to the papers and copies of slides from the authors' talks.

Note: It is possible that your version of ghostview may have some trouble viewing some of these postscript files, but they should all print okay. If you have any problems, send mail to webmaster@iram.cs.berkeley.edu

Workshop notes: There are notes available from the workshop, thanks to Ben Gribstad. Links to the appropriate topics within the notes are also provided below at the appropriate sections as well as for individual papers.

Feedback summary: A summary of the feedback obtained from attendees at the workshop was collated by Liz Pennell.

List of attendees: A list of the attendees at the workshop, along with their affiliation, is now available.

8:30am Welcoming Remarks

8:45am Beyond the Desktop

1. Evaluation of Existing Architectures in IRAM Systems, Ngeci Bowman, Neal Cardwell, Christoforos E. Kozyrakis, Cynthia Romer, and Helen Wang (University of California, Berkeley), IRAM Project, paper , slides , notes
2. The Smart Access Memory: An Intelligent RAM for Nearest Neighbor Database Searching, Aaron Lipman and Woodward Yang (Harvard University). paper , slides , notes
3. IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck, Kimberly Keeton, Remzi Arpaci-Dusseau, and David A. Patterson (University of California at Berkeley), IRAM, NOW-Sort. paper , slides , notes

4. IRAM Design for Multimedia Applications, Bum-Sik Kim and Lee-Sup Kim (Korea Advanced Institute of Science and Technology). paper

10:15am Break

10:45am SIMD and Vector Approaches

1. Computational RAM: The case for SIMD computing in memory, Duncan Elliott (University of Alberta), Michael Stumm (University of Toronto), and Martin Snelgrove (Carleton University), C-RAM Project. paper , slides , notes
2. Distributed Vector Architecture: Beyond a Single Vector-IRAM, Stefanos Kaxiras (University of Wisconsin-Madison), Rabin Sugumar and James Schwarzmeier (CRAY Research), DIVA. paper , slides , notes
3. Using MML to Simulate Multiple Dual-Ported SRAMs: Parallel Routing Lookups in an ATM Switch Controller, Aaron Brown, Dan Chian, Nishat Mehta, Yannis Papaefstathiou, Josh Simer, Trevor Blackwell, Michael D. Smith, and Woodward Yang (Harvard University). paper , slides , notes

4. Considerations Leading to an Asynchronous SIMD Architectural Approach for Exploiting Mixed Logic and Memory, Charles Weems (University of Massachusetts). paper , slides

12:15pm Lunch - on your own

1:45pm Multiprocessors

1. How Processor-Memory Integration Affects the Design of DSMs, Liuxi Yang, Anthony-Trung Nguyen, and Josep Torrellas (University of Illinois at Urbana-Champaign), I-ACOMA multiprocessor project. paper , slides , notes
2. A Single Chip Multiprocessor Integrated with DRAM, Tadaaki Yamauchi (Mitsubishi), Lance Hammond, and Kunle Olukotun (Stanford University). paper , slides , notes
3. A Multiprocessor Memory Processor for Efficient Sharing and Access Coordination, David M. Koppelman (Louisiana State University). paper , slides , notes

4. Efficient Use of Processing Transistors for Larger On-Chip Storage: Multithreading, Venkata Krishnan and Josep Torrellas (University of Illinois at Urbana-Champaign). paper

3:15pm Break

3:45pm Limits and the Future

1. The Relative Importance of Memory Latency, Bandwidth, and Branch Limits to Performance, Norman P. Jouppi (Digital Equipment Corporation) and Parthasarathy Ranganathan (Rice University). paper , slides , notes
2. Processing In Memory: Chips to Petaflops, Peter M. Kogge, Jay B. Brockman (University of Notre Dame), Thomas Sterling (California Institute of Technology), Guang Gao (University of Delaware). paper , slides , notes

3. On-Chip Memorypath Architectures for Parallel Processing RAM (PPRAM), Hiroshi Miyajima, Koji Inoue, Koji Kai, and Kazuaki Murakami (Kyushu University). paper
4. System-Level Implications of Processor-Memory Integration, Doug Burger (University of Wisconsin-Madison), Galileo project. paper

4:45pm Open-mike session

• Corinna Lee, Toronto, Computational Power of Vector processing, notes
• Mateo Valero, Barcelona, Vector + IRAM, notes
• Yunho Choi, Samsung, Technology, notes
• Steve Przbylski, Consultant, Money and Memory, notes
• Kevin Kissel, SGI , IRAM: The "right" Way and The "Wrong" Way, notes
• Chip Weems, Umass/Amherst, Fallacies and pitfalls for SIMD-IRAM, notes
• Barry Fagin, Relevance of "Whack-a-Mole" to IRAM (an observer's perspective), notes

5:15pm Wrap-up

6:30pm ISCA'97 Welcoming Reception

Go to ISCA '97 web page