"VIRAM1: A Media-Oriented Vector Processor with Embedded DRAM", J. Gebis, S. William, C. Kozyrakis, D. Patterson. 41st Design Automation Student Design Contenst, San Diego, CA, June 2004. pdf
"Overcoming the Limitations of Conventional Vector Processors", C. Kozyrakis, D. Patterson. 30th International Symposium on Computer Architecture, San Diego, CA, June 2003. pdf
"Vector Vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks," C. Kozyrakis, D. Patterson. 35th International Symposium on Microarchitecture, Instabul, Turkey, November 2002. pdf
"Scalable Vector Media-processors for Embedded Systems", Report No. UCB/CSD-02-1183, University of California, Berkeley, May 2002. pdf
"Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines," Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leonid Oliker, Katherine A. Yelick, and Rupak Biswas. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS). Ft. Lauderdale, FL. April, 2002. pdf
"Hardware/Compiler Co-development for an Embedded Media Processor," C. Kozyrakis, D. Judd, J. Gebis, S. Williams, D. Patterson, K. Yelick, Proceedings of the IEEE, vol. 89, no. 11, November 2001 (p. 1694-709). pdf
"Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler," D. Judd, K. Yelick, C. Kozyraki, D. Martin, and D. Patterson, Second Workshop on Intelligent Memory Systems, Cambridge, November 2000. postscript.
"Performance Analysis of an H.263 Video Encoder on VIRAM," T. Nguyen, A. Zakhor and K. Yelick International Conference on Image Processing (ICIP), Vancouver, B.C., Canada, September 2000. pdf
"Vector IRAM: A Media-oriented Vector Processor with Embedded DRAM," C. Kozyrakis, J. Gebis, D. Martin, S. Williams, I. Mavroidis, S. Pope, D. Jones, D. Patterson, K. Yelick. 12th Hot Chips Conference, Palo Alto, CA, August 2000. pdf
"An Architectural Performance Study of the Fast Fourier Transform on Vector IRAM", Technical Report UCB/CSD-00-1106, University of California, Berkeley, June 2000. ps (1400K) pdf (542K)
"Efficient FFTs On VIRAM." Proceeding of the
1st Workshop on Media Processors and DSPs,
in Conjunction with the
32nd Annual International Symposium on Microarchitecture, Haifa, Israel, November 15, 1999. postscript (357K) pdf (108K)
"A Media-Enhanced Vector Architecture for Embedded Memory Systems", Technical Report UCB//CSD-99-1059, University of California, Berkeley, July 1999. pdf (217K)
"A New Direction in Computer Architecture Research", IEEE Computer November 1998. pdf (384K)
"Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architecture", ICCD '97 International Conference on Computer Design, Austin, Texas, 10-12 October 1997. postscript (111K) pdf (30K)
"Evaluation of Existing Architectures in IRAM Systems", W. Bowman, N. Cardwell, C. Kozyrakis, C. Romer, and H. Wang. Workshop on Mixing Logic and DRAM, 24th International Symposium on Computer Architecture, June 1997. postscript
"Scalable Processors in the Billion Transistor Era: IRAM", IEEE Computer Special Issue: Future Microprocessors - How to use a Billion Transistors, September 1997. pdf (85K)
"IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck" Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97, Denver, CO, 1 June 1997. postscript
"The Energy Efficiency of IRAM Architectures," ISCA '97: The 24th Annual International Symposium on Computer Architecture , Denver, CO, 2-4 June 1997. postscript.
"A Case for Intelligent DRAM: IRAM," IEEE Micro , April 1997. postscript (655K) pdf (89K).
"Intelligent RAM (IRAM): Chips that remember and compute," 1997 IEEE International Solid-State Circuits Conference , San Francisco, CA, 6-8 February 1997. postscript (67K) pdf (16K).
"Intelligent RAM (IRAM): Chips that Remember and Compute" Revised. Presented at the Industrial Liason Program (ILP) meeting on March 12, 1997 at U.C. Berkeley and at the DARPA Embbedded Systems Principle Investigator meeting on March 21, 1997 in Santa Fe, New Mexico. Slides: postscript (770K), pdf (72K), powerpoint binary for mac (127K).
"Intelligent RAM (IRAM): Chips that Remember and Compute" Presented at the 1997 IEEE International Solid-State Circuits Conference (ISSCC) 6-8 February 1997, San Francisco, CA. Abstract, Slides: postscript (747K), pdf (54K).
"A Case for Intelligent DRAM: IRAM," Presented at Hot Chips VIII, Palo Alto CA., 18-20 August 1996. postscript (585K) pdf (256K)
" Holy Grail of embedded DRAM challenged," EE Times, June 23, 1997.
" What will be the legacy of RISC?," EE Times, May 12, 1997.
"Intelligent RAM: The coming convergence of memory and processors," Wired, August 1996. Page 1/1 (230K jpeg).
Selected traffic from the Usernet newsgroup comp.arch concerning "Processors in Memory", compiled in Computer Architecture News, June 1996. Pages 1 2 3 4 (180K jpeg each).
Patterson, D., "Microprocessors in 2020," Scientific American, September 1995. Pages 1, 2, 3, 4 (200K jpeg each).