IRAM Serial I/O Project: Final Project Report

The Design of a High Speed Serial Link for IRAM

Turi Aytur, Joe Gebis, Jason Golbus,
Ben Gribstad, Cheol-Woong Lee, Jianjin Tuan

CS 254 Project Report



High performance, low power, low pin count communication is highly desirable in an IRAM system. We propose an architecture for the physical layer of a serial link which will run at 1Ghz and have a data bandwidth of 0.8 Gbit/s with low power dissipation and small pin requirements. We examine the tradeoffs with various circuit topologies for each functional block in the link. Area, power, and performance is calculated for the entire link and compared with results from similar work. The total area for the link minus the two large loop filters is estimated to be 0.45mm2 and consume approximately 86mW of power.

  1. Introduction
  2. Discussion of Blocks
    1. Clock Phase Generation
    2. Phase Interpolator
    3. IBM 8b/10b Encoder and Decoder
    4. Control Logic
    5. Serializer
    6. Transmitter, Receiver and Sampler
  3. Area and Power Summary
  4. Conclusions
  5. References